🟢Introduction to SystemVerilog

Verilog se SystemVerilog transition.

• Why SystemVerilog?

• RTL + Verification overview

• SV data types

• logic vs reg

• arrays

• packed/unpacked arrays

🟢SystemVerilog OOP Concepts

Verification programming foundation.

• Classes

• Objects

• Constructors

OOP Features:

• Encapsulation

• Inheritance

• Polymorphism

Methods:

• virtual functions

• static members

🟢Randomization & Constraints

Constrained random verification.

• rand / randc

• Constraints

• Constraint blocks

• inline constraints

Advanced:

• Constraint modes

• soft constraints

• Distribution constraints

🟢Interprocess Communication

• Mailbox

• Semaphore

• Events

🟢Functional Coverage

Coverage-driven verification.

• Covergroup

• Coverpoint

• Bins

• Cross coverage

🟢Assertions (SVA)

Design checking automation.

• Immediate assertions

• Concurrent assertions

• Properties

• Sequences

🟢Testbench Architecture

Industry-style verification environment.

• Generator

• Driver

• Monitor

• Scoreboard

• Environment

Concepts:

• Transaction-based verification

• Reusable TB architecture

🟢Interface & Clocking Blocks

• Interface

• Modports

• Clocking blocks

• Virtual interface

🟢UVM Introduction (Optional Advanced)

Industry exposure.

• UVM overview

• UVM components

• Sequence & Sequencer

• Driver & Monitor

• Factory mechanism

👉 Basic exposure enough for training level