M A S T E R I N G V L S I L O G I C

Go4VLSI

VERILOG HDL

  • Comprehensive Curriculum

  • Toolchain Training

  • Hands-on Projects

  • Exposure to industry-standard tools

🔹Basics of Digital Electronics
  • Number systems (Binary, Hex, Octal)

  • Logic gates (AND, OR, NOT, NAND, NOR, XOR)

  • Boolean algebra

  • Combinational vs Sequential circuits

🔹Introduction to Verilog HDL
  • Verilog kya hai aur kyu use hota hai

  • Structure of Verilog module

  • Data types (wire, reg, integer, parameter)

  • Operators (arithmetic, logical, relational)

🔹Modeling Styles in Verilog
  • Gate-level modeling

  • Dataflow modeling

  • Behavioral modeling

🔹Combinational Circuit Design
  • Multiplexer, Demultiplexer

  • Encoder, Decoder

  • Adders (Half, Full, Ripple Carry)

  • Comparator

🔹Sequential Circuit Design
  • Flip-flops (D, JK, T)

  • Registers

  • Counters (Up/Down)

  • Shift registers

🔹Procedural Blocks
  • always block

  • initial block

  • Blocking vs Non-blocking assignments

  • Case & If statements

🔹Finite State Machines (FSM)
  • Mealy vs Moore machine

  • State diagram & state table

  • FSM design using Verilog

🔹Testbench & Simulation
  • What is a Testbench

  • Stimulus generation

  • $display, $monitor

  • Simulation tools (ModelSim, Vivado)

🔹Timing & Delays
  • #delay

  • Timing control

  • Race conditions

🛠️ Practical / Lab Work
  • Basic gate implementation

  • MUX, Adder design

  • Counter design

  • FSM design

  • Testbench writing

  • Simulation on tools